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DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter AD8333
FEATURES
Dual integrated I/Q demodulator 16 phase select on each output (22.5 per step) Quadrature demodulation accuracy Phase accuracy: 0.1 Amplitude balance: 0.05 dB Bandwidth 4 LO: 100 kHz to 200 MHz RF: dc to 50 MHz Baseband: determined by external filtering Output dynamic range: 161 dB/Hz LO drive > 0 dBm (50 ); 4 LO > 1 MHz Supply: 5 V Power consumption: 190 mW/channel (380 mW total) Power down
FUNCTIONAL BLOCK DIAGRAM
CH1 PHASE SELECT + - 0 I1
CH1 RF
AD8333
90 LOC OSC /4 90 Q2 Q1
0 CH2 RF + -
I2
Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers
Figure 1.
GENERAL DESCRIPTION
The AD8333 is a dual-phase shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable for beamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the AD8332. A divide-by-four circuit generates the internal 0 and 90 phases of the LO that drive the mixers of a pair of matched I/Q demodulators. The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment. The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5 increments can be selected independently for each channel. For example, if CH1 is used as a reference and the RF signal applied to CH2 has an I/Q phase lead of 45, then the user can phase align CH2 with CH1 by choosing the correct code. Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5. The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic-range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS). The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator. The dynamic range is 161 dB/Hz at each I and Q output, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design. The AD8333 is available in a 32-lead LFCSP (5 mm x 5 mm) package for the industrial temperature range of -40C to +85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05543-001
APPLICATIONS
CH2 PHASE SELECT
AD8333 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Equivalent Input Circuits ................................................................ 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 14 Theory of Operation ...................................................................... 17 Quadrature Generation ............................................................. 17 I/Q Demodulator and Phase Shifter ........................................ 17 Dynamic Range and Noise........................................................ 18 Summation of Multiple Channels (Analog Beamforming).. 19 Phase Compensation and Analog Beamforming................... 19 Channel Summing ..................................................................... 20 Dynamic Range Inflation .......................................................... 22 Disabling the Current Mirror and Decreasing Noise............ 22 Applications..................................................................................... 24 Logic Inputs and Interfaces....................................................... 24 Reset Input .................................................................................. 24 Connecting to the LNA of the AD8331/ AD8332/AD8334/AD8335 VGAs............................................ 24 LO Input ...................................................................................... 25 Evaluation Board ........................................................................ 25 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
5/06--Rev. 0 to Rev. A Changes to Figure 62...................................................................... 26 10/05--Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8333 SPECIFICATIONS
VS = 5 V, TA = 25C, 4 fLO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO 0 dBm, single-ended, sine wave; per channel performance, dBm (50 ), unless otherwise noted (see Figure 41). Table 1.
Parameter OPERATING CONDITIONS LO Frequency Range Conditions 4x internal LO at Pin 4LOP and Pin 4LON Square wave Sine wave, see Figure 22 Mixing Limited by external filtering See Figure 22 Min Typ Max Unit
RF Frequency Range Baseband Bandwidth LO Input Level VSUPPLY (VS) Temperature Range DEMODULATOR PERFORMANCE RF Differential Input Impedance LO Differential Input Capacitance Transconductance
0.01 2 DC DC 4.5 -40 0 5
200 200 50 50 13 6 +85
MHz MHz MHz MHz dBm V C k||pF pF
6.7||6.5 0.6 Demodulated IOUT/VIN, each Ix or Qx output after low-pass filtering measured from RF inputs All phases IP1dB, input referred noise (dBm) Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN 0 phase shift 45 phase shift Ref = 50 Ref = 1 VRMS fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Baseband tones: -7 dBm @ 8 kHz and 13 kHz Baseband tones: -1 dBm @ 8 kHz and -31 dBm @ 13 kHz Same conditions as IM3 Measured at RF inputs, worst phase, measured into50 (limited by measurement) Measured at baseband outputs, worst phase, 8021 disabled, measured into 50 All codes, see Figure 41 Output noise/conversion gain, see Figure 41 Output noise / 787 With AD8332 LNA RS = 50 , RFB = RS = 50 , RFB = 1.1 k RS = 50 , RFB = 274 Pin 4LOP and Pin 4LON Pin RFxP and Pin RFxN Pin 4LOP and Pin 4LON (each pin) For maximum differential swing; Pin RFxP and Pin RFxN (dc-coupled to AD8332 LNA output) Pin IxPO and Pin QxPO
Dynamic Range Maximum RF Input Swing Peak Output Current (No Filtering) Input P1dB Third-Order Intermodulation (IM3) Equal Input Levels Unequal Input Levels Third-Order Input Intercept (IP3) LO Leakage
2.17 161 2.8 4.7 6.6 14.5 1.5 -75 -77 30 <-97 -60 4.7 10 22 7.8 9.0 11.0 -3 -70 0.2 2.5 -1.5 +0.7 3.8
mS dB/Hz V p-p mA mA dBm dBV dBc dBc dBm dBm dBm dB nV/Hz pA/Hz dB dB dB A A V V V
Conversion Gain Input Referred Noise Output Current Noise Noise Figure
Bias Current LO Common-Mode Voltage Range RF Common-Mode Voltage Output Compliance Range
Rev. A | Page 3 of 28
AD8333
Parameter PHASE ROTATION PERFORMANCE Phase Increment Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching LOGIC INTERFACES Logic Level High Logic Level Low Bias Current Pin PHxx and Pin ENBL Pin RSET Input Resistance Reset Hold Time Minimum Reset Pulse Width Reset Response Time Phase Response Time Enable Response Time POWER SUPPLY Supply Voltage Quiescent Current, All Phase Bits = 0 Conditions One CH is reference, other is stepped 16 phase steps per channel I1 to Q1 and I2 to Q2, 1 I1 to Q1 and I2 to Q2, 1 Phase match I1/I2 and Q1/Q2; -40C < TA < 85C Amplitude match I1/I2 and Q1/Q2; -40C < TA < 85C Pin PHxx, Pin RSET, and Pin ENBL Pin PHxx, Pin RSET, and Pin ENBL Logic high Logic low Logic high Logic low Pin PHxx and Pin ENBL Pin RSET Reset is asynchronous; clock disabled when RSET goes HI until 300 ns after RSET goes LO See Figure 35 See Figure 38 See Figure 34 Pin VPOS and Pin VNEG 4.5 @25C Pin VPOS Pin VNEG -40C < TA < 85C Pin VPOS, all phase bits = 0 Pin VNEG Per channel, all phase bits = 0 Per channel, any 0 or 1 combination of phase bits All channels disabled Pin VPOS Pin VNEG PSRR Pin VPOS to Ix/Qx outputs (measured @ AD8021 output) Pin VNEG to Ix/Qx outputs (measured @ AD8021 output) -81 -75 dB dB 38 -24 40 -24 170 190 Min Typ Max Unit
-2
22.5 0.1 0.05 1 0.25
+2
Degrees Degrees dB Degrees dB V V A A A A k k ns ns ns s ns
1.7 0 10 -30 50 -70 40 -7 120 -20 60 20
5 1.3 90 +10 180 0
300 300 300 5 300 5 44 -20 6 51 -16 54 -19
V mA mA mA mA mW mW
Over Temperature
Quiescent Power Disable Current
1.0 -300
1.25 -200
1.5 -100
mA A
Rev. A | Page 4 of 28
AD8333 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Voltages Supply Voltage VS RF Pins Input LO Inputs Code Select Inputs V Thermal Data--4-Layer JEDEC Board No Air Flow (Exposed Pad Soldered to PC Board) JA JB JC JT JB Maximum Junction Temperature Maximum Power Dissipation (Exposed Pad Soldered to PC Board) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 6V VS, GND VS, GND VS, GND
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
41.0C/W 23.6C/W 4.4C/W 0.4C/W 22.4C/W 150C 1.5 W -40C to +85C -65C to +150C 300C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 28
AD8333 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PH11 PH10 VPOS RF1P RF1N VPOS ENBL I1NO
29 28 27 26 31
PH12 PH13 COMM 4LOP 4LON LODC PH23 PH22
32
30
25
1 2 3 4 5 6 7 8
24
PIN 1 INDICATOR TOP VIEW (Not to Scale)
23 22 21 20 19 18 17
AD8333
I1PO Q1PO Q1NO VNEG COMM Q2NO Q2PO I2PO
11
9
PH21 PH20 VPOS RF2P RF2N VPOS RSET I2NO
16
10
12
13
14
15
Figure 2. 32-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 2, 7, 8 3, 20 4, 5 Mnemonic PH12, PH13 PH23, PH22 COMM 4LOP, 4LON Description Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0 to 90, 90 to180, 180 to 270, 270 to 360 (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Ground. These two pins are internally tied together. LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum performance, these inputs should be driven differentially with a signal level that is not less than what is shown in Figure 22. Bias current is only -3 A. Single-ended drive is also possible if the inputs are biased correctly (see Figure 4). Decoupling Pin for LO. A 0.1 F capacitor should be connected between this pin and ground (see Figure 5). Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0, 22.5, 45, 67.5 (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 F and 100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set of supply decoupling components for all four pins should be sufficient. RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to the output pins of the AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input differential swing is 2.5 V if 5 V supplies are used (see Figure 6). Reset for Divide-by-Four in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Negative I/Q Outputs. These outputs are not connected for normal usage but can be used for filtering if needed. Together with the positive I/Q outputs, they allow bypassing the internal current mirror if a lower noise output circuit is available; VNEG needs to be tied to GND to disable the current mirror (see Figure 7). Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a transimpedance amplifier. Multiple outputs can be summed together by simply connecting them together. The bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 7). Negative Supply. This pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 F and 100 pF capacitor between the pin and ground. Chip Enable. Logic threshold is at about 1.5 V and therefore it can be driven by 3 V CMOS logic (see Figure 3).
6 9, 10, 31, 32 11, 14, 27, 30 12, 13, 28, 29 15 16, 19, 22, 25 17, 18, 23, 24 21 26
LODC PH21, PH20 PH10, PH11 VPOS
RF2P, RF2N RF1N, RF1P RSET I2NO, Q2NO Q1NO, I1NO I2PO, Q2PO Q1PO, I1PO VNEG ENBL
Rev. A | Page 6 of 28
05543-002
AD8333 EQUIVALENT INPUT CIRCUITS
VPOS
VPOS
PHxx ENBL RSET
LOGIC INTERFACE
RFxP
RFxN
05543-003
COMM
COMM
Figure 3. Logic Inputs
VPOS
Figure 6. RF Inputs
COMM
4LOP
IxNO QxNO IxPO QxPO
4LON
05543-004
COMM
VNEG
Figure 4. Local Oscillator Inputs
VPOS
Figure 7. Output Drivers
LODC
COMM
Figure 5. LO Decoupling Pin
05543-005
Rev. A | Page 7 of 28
05543-007
05543-006
AD8333 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25C, 4fLO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO 0 dBm (50 ); single-ended sine wave; per channel performance, differential voltages, dBm (50 ), phase select code = 0000, unless otherwise noted (see Figure 41).
1.5 f = 1MHz Q I
2
CODE 0100 CODE 0011 CODE 0010
PHASE ERROR (Degrees)
f = 5MHz 1 0 -1 -2 2 f = 1MHz 1 0
05543-008
1.0
IMAGINARY (Normalized)
CODE 0001 0.5 CODE 1000 0 CODE 0000
-0.5
-1.0 CODE 1100 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
-1.5 -2.0
REAL (Normalized)
-2 0000
0010
0100
0110
1000
1010
1100
1110
1111
CODE (Binary)
Figure 8. Normalized Vector Plot of Phase, CH2 with Respect to CH1; CH1 Is Fixed at 0, CH2 Stepped 22.5/Step, All Codes Displayed
360 315 270
PHASE (Degrees)
Figure 11. Phase Error of CH2 with Respect to CH1 vs. Code at 1 MHz and 5 MHz
500mV
1MHz 5MHz
225 180 135 90
05543-009
45 0 0000
20s
0010
0100
0110
1000
1010
1100
1110
1111
CODE (Binary)
Figure 9. Phase of CH2 with Respect to CH1 vs. Code, at 1 MHz and 5 MHz
1.0 f = 5MHz 0.5 0
AMPLITUDE ERROR (dB)
Figure 12. I or Q Output of CH2 with Respect to CH1, First Quadrant Shown
7
CHANNEL 1, I OUTPUT SHOWN
6
CODE 0000 CODE 0001 CODE 0010 CODE 0011
-0.5 -1.0 1.0 f = 1MHz 0.5 0
05543-010
GAIN (dB)
5
4
05543-013
-0.5 -1.0 0000
0010
0100
0110
1000
1010
1100
1110
1111
3 1M
10M RF FREQUENCY (Hz)
05543-012
50M
CODE (Binary)
Figure 10. Amplitude Error of CH2 with Respect to CH1 vs. Code at 1 MHz and 5 MHz
Figure 13. Conversion Gain vs. RF Frequency, First Quadrant, Baseband Frequency = 10 kHz
Rev. A | Page 8 of 28
05543-011
-1
AD8333
2.0
QUADRATURE PHASE ERROR (Degrees)
0.5 0.4
I/Q AMPLITUDE IMBALANCE (dB)
1.5 1.0 0.5 0 -0.5 -1.0
05543-014
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 100 1k 10k
05543-017
-1.5 -2.0 1M
10M RF FREQUENCY (Hz)
100M
100k
BASEBAND FREQUENCY (Hz)
Figure 14. Representative Range of Quadrature Phase Errors vs. RF Frequency, CH1 or CH2, All Codes
2.0
QUADRATURE PHASE ERROR (Degrees)
Figure 17. Representative Range of I/Q Amplitude Imbalance vs. Baseband Frequency, CH1 and CH2 ( see Figure 43)
2.0 1.5 CODE 0000 -40C +25C +85C CODE 0001 -40C +25C +85C
1.5
fBB =10kHz I2/I1 DISPLAYED
AMPLITUDE ERROR (dB)
1.0 0.5 0 -0.5 -1.0
05543-015
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 1M
CODE 0010 -40C +25C +85C CODE 0011 -40C +25C +85C 10M RF FREQUENCY (Hz)
-2.0 100
1k
10k
100k
50M
BASEBAND FREQUENCY (Hz)
Figure 15. Range of Quadrature Phase Error vs. Baseband Frequency, CH1 and CH2 ( see Figure 43)
0.5 0.4
I/Q AMPLITUDE IMBALANCE (dB)
Figure 18. Typical I2/I1 or Q2/Q1 Amplitude Match vs. RF Frequency First Quadrant, at Three Temperatures
8 CODE 0000 -40C +25C +85C CODE 0001 -40C +25C +85C CODE 0010 -40C +25C +85C CODE 0011 -40C +25C +85C
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M 10M RF FREQUENCY (Hz)
05543-016
6
PHASE ERROR (Degrees)
4
2
0
-2 fBB = 10kHz I2/I1 DISPLAYED -4 1M 10M RF FREQUENCY (Hz)
05543-043
50M
50M
Figure 16. Representative Range of Amplitude Imbalance of I/Q vs. RF Frequency, CH1 or CH2, All Codes
Figure 19. I2/I1 or Q2/Q1 Phase Error vs. RF Frequency, Baseband Frequency = 10 kHz, at Three Temperatures
Rev. A | Page 9 of 28
05543-018
-1.5
AD8333
2.8 2.7 CHANNEL 1, I OUTPUT SHOWN TRANSCONDUCTANCE = [(VBB/787)V RF] 10 GAIN = VBB/VRF 5 0 CODE 0000 CODE 0001 CODE 0010 CODE 0011 -5 +85C +25C -40C
TRANSCONDUCTANCE (ms)
2.6 2.5 2.4 2.3 2.2
05543-020
GAIN (dB)
-10 -15 -20
05543-019
2.1 2.0 1M
-25 -30
10M RF FREQUENCY (Hz)
50M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
COMMON-MODE VOLTAGE (V)
Figure 20. Transconductance vs. RF Frequency, First Quadrant
10 0 -10 -20
IP1dB (dBm) GAIN (dB)
Figure 23. LO Common-Mode Range at Three Temperatures
20 18
f = 5MHz GAIN = VBB/VRF
16 14 12 10 8 6 4
05543-021
-30 -40 -50 -60 -70 -80 -20 CODE 0000 CODE 0001 CODE 0010 CODE 0011
2 0 1M 10M RF FREQUENCY (Hz)
-15
-10 POWER (dBm)
-5
0
50M
Figure 21. Conversion Gain vs. LO Level, First Quadrant
Figure 24. IP1dB vs. Frequency, Baseband Frequency = 10 kHz, First Quadrant (see Figure 42)
0
5 0
MINIMUM LO LEVEL (dBm)
ALL CODES
BOTH CHANNELS -10 REGION OF USEABLE LO LEVELS
IM3 (dBc)
-5 -10 -15 -20 -25 -30
-20 -30 -40 -50 -60 -70
05543-022
-7dBm 3 8 13 18 IM3 PRODUCTS LO = 5.023MHz RF1 = 5.015MHz RF2 = 5.010MHz
-40 100k
1M
10M FREQUENCY (Hz)
100M
-90 1M
10M RF FREQUENCY (Hz)
50M
Figure 22. Minimum LO Level vs. RF Frequency, Single-Ended, Sine Wave LO Drive to Pin 4LOP or Pin 4LON
Figure 25. Representative Range of IM3 vs. RF Frequency, First Quadrant (see Figure 49)
Rev. A | Page 10 of 28
05543-024
-35
-80
05543-023
AD8333
40 BOTH CHANNELS 35 30 25 20 15 10
05543-025
0 LO LEVEL = 0dBm -20 -40 -60 -80 -100 -120 -140 1M
LO LEAKAGE (dBm)
OIP3 (dBm)
RF1P RF2P RF1N RF2N
0 1M
10M RF FREQUENCY (Hz)
50M
10M RF FREQUENCY (Hz)
50M
Figure 26. Representative Range of OIP3 vs. RF Frequency, First Quadrant (see Figure 49)
35 30 25
NOISE (nV/ Hz) OIP3 (dBm)
Figure 29. LO Leakage vs. RF Frequency at RF Inputs
16 14 12 CHANNEL 1 RF CHANNEL 2 RF 10 8 6 4
05543-026
-142.9 -144.1 -145.4
NOISE (dBm)
05543-064
05543-029
I1 Q1
-147.0 -148.9 -151.4 -154.9 -161.0
20 15 10 5 0 1k
2 0 1M
10k BASEBAND FREQUENCY (Hz)
100k
10M RF FREQUENCY (Hz)
50M
Figure 27. OIP3 vs. Baseband Frequency (see Figure 48)
0 LO LEVEL = 0dBm -10 -20
LO LEAKAGE (dBm)
20 18 16
Figure 30. Input Referred Noise vs. RF Frequency
-30 -40 -50 -60
I1 I2 Q1 Q2
NOISE FIGURE (dB)
14 12 10 8 6 4
05543-027
-70 -80 1M
2 0 1M 10M RF FREQUENCY (Hz)
10M RF FREQUENCY (Hz)
50M
50M
Figure 28. LO Leakage vs. RF Frequency at Baseband Outputs
Figure 31. Noise Figure vs. RF Frequency with AD8332 LNA
Rev. A | Page 11 of 28
05543-028
5
AD8333
172 170 168
DYNAMIC RANGE (dB)
I1 Q1 I1 + I2 Q1 + Q2
2V
166 164 162 160 158 156 154 152 1M 10M RF FREQUENCY (Hz)
05543-030
500mV
200ns
50M
Figure 32. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level, Single Channel and Two Channels Summed
6 4 GAIN = VBB/VRF 2 0
GAIN (dB)
Figure 35. Reset Response--Top: Signal at Reset Pin Bottom: Output Signal (see Figure 45)
5V
CODE 0000 CODE 0010
-2 -4 -6
05543-044
1V
1V
40s
-10 -3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
VOLTAGE (V)
Figure 33. Output Compliance Range (IxPO, QxPO) (see Figure 50)
Figure 36. Phase Switching Response--CH2 Leads CH1 by 45, Top: Input to PH21, Select Code = 0010 Red: Ref CH1 IOUT; Gray: CH2 IOUT Phase Shifted 45, CH1 Ref Phase Select Code = 0000
5V
500mV
05543-045
2V
200ns
1V
1V
40s
Figure 34. Enable Response--Top: Enable Signal Bottom: Output Signal (see Figure 44)
Figure 37. Phase Shifting Response--CH2 Leads CH1 by 90, Top: Input to PH21, Select Code = 0100 Red: Ref CH1 IOUT, Gray: CH2 IOUT Phase Shifted 90, CH1 Ref Phase Code = 0000
Rev. A | Page 12 of 28
05543-048
05543-047
-8
05543-046
AD8333
60 5V 50 VPOS
SUPPLY CURRENT (mA)
40
30
20
VNEG
05543-049
10
05543-051
1V
1V
40s
0 -50
-30
-10
10
30
50
70
90
TEMPERATURE (C)
Figure 38. Phase Shifting Response--CH2 Leads CH1 by 180, Top: Input to PH23 Select Code = 1000 Red: Ref CH1 IOUT, Gray: CH2 IOUT Phase Shifted 180, CH1 Ref Phase Code = 0000
0 -10 -20 -30
PSRR (dB)
Figure 40. Quiescent Supply Current vs. Temperature
-40 -50 -60 -70 -80 -90 100k VNEG VPOS
05543-050
1M FREQUENCY (Hz)
10M
50M
Figure 39. PSRR vs. Frequency (see Figure 51)
Rev. A | Page 13 of 28
AD8333 TEST CIRCUITS
AD8021
120nH 0.1F FB LPF 50 SIGNAL GENERATOR 0.1F
AD8332
LNA 20 RFxP Ix
787 2.2nF 2.2nF OSCILLOSCOPE
AD8333
20 RFxN LOP Qx
787
50
05543-032
SIGNAL GENERATOR
AD8021
Figure 41. Default Test Circuit
AD8021
120nH 0.1F FB LPF 50 SIGNAL GENERATOR 0.1F
AD8332
LNA 20 RFxP Ix
100 10nF 10nF OSCILLOSCOPE
AD8333
20 RFxN LOP Qx
100
50
05543-033
SIGNAL GENERATOR
AD8021
Figure 42. P1dB Test Circuit
AD8021
120nH 1F FB LPF 50 SIGNAL GENERATOR 1F 20
AD8332
LNA 20 RFxP Ix Qx 787 787 OSCILLOSCOPE
AD8333
RFxN LOP
50 SIGNAL GENERATOR
AD8021
05543-034
Figure 43. Phase and Amplitude vs. Baseband Frequency
Rev. A | Page 14 of 28
AD8333
AD8021
120nH 1F FB LPF 50 SIGNAL GENERATOR 1F 20
AD8332
LNA 20 RFxP Ix Qx LOP 787 787 OSCILLOSCOPE
AD8333
RFxN ENBL
50 SIGNAL GENERATOR
50
AD8021
05543-035
SIGNAL GENERATOR
Figure 44. Enable Response
AD8021
120nH 1F FB LPF 50 SIGNAL GENERATOR 1F 20
AD8332
LNA 20 RFxP Ix Qx LOP 787 787 OSCILLOSCOPE
AD8333
RFxN RST
50 SIGNAL GENERATOR
50
AD8021
05543-036
SIGNAL GENERATOR
Figure 45. Reset Response
AD8332
LNA 20 RFxP Ix OSCILLOSCOPE
120nH FB 0.1F LPF 50 SIGNAL GENERATOR 0.1F
AD8333
20 RFxN LOP Qx
50 50
50
05543-037
SIGNAL GENERATOR
Figure 46. RF Input Range
AD8021
6.98k RFxP 0.1F 270pF Ix 270pF Qx 6.98k SPECTRUM ANALYZER
AD8333
RFxN LOP
50
05543-052
SIGNAL GENERATOR
AD8021
Figure 47. Noise Test Circuit
Rev. A | Page 15 of 28
AD8333
AD8021
50 SIGNAL GENERATOR
COMBINER AD8332 -6dB 120nH LNA 20 0.1F FB
787 RFxP 100pF Ix 100pF Qx 787 SPECTRUM ANALYZER
AD8333
50 SIGNAL GENERATOR 50 0.1F 20 RFxN LOP
Figure 48. OIP3 vs. Baseband Frequency
AD8021
50 SIGNAL GENERATOR
COMBINER AD8332 -6dB 120nH LNA 20 0.1F FB
787 RFxP 2.2nF Ix 2.2nF Qx 787 SPECTRUM ANALYZER
AD8333
50 SIGNAL GENERATOR 50 0.1F 20 RFxN LOP
Figure 49. OIP3 and IM3 vs. RF Frequency
AD8021
120nH 0.1F FB LPF 50 SIGNAL GENERATOR 0.1F
AD8332
LNA 20 RFxP Ix
787 2.2nF 2.2nF OSCILLOSCOPE
AD8333
20 RFxN LOP Qx
787
50
05543-055
SIGNAL GENERATOR
AD8021
Figure 50. Output Compliance Range
AD8332
LNA 20 RFxP Ix Qx NETWORK ANALYZER
120nH 0.1F FB LPF 50 SIGNAL GENERATOR 0.1F
AD8333
20 RFxN LOP
50
05543-056
SIGNAL GENERATOR
Figure 51. PSRR Test Circuit
Rev. A | Page 16 of 28
05543-054
SIGNAL GENERATOR
AD8021
05543-053
SIGNAL GENERATOR
AD8021
AD8333 THEORY OF OPERATION
The AD8333 is a dual I/Q demodulator with a programmable phase shifter for each channel. The primary applications are phased array beamforming in medical ultrasound, phased array radar, and smart antennas for mobile communications. The AD8333 can also be used in applications that require two wellmatched I/Q demodulators. Figure 52 shows the block diagram and pinout of the AD8333. Three analog and nine quasi-logic level inputs are required. Two RF inputs accept signals from the RF sources and a local oscillator (applied to the differential input pins marked 4LOx) common to both channels comprise the analog inputs. Four logic inputs per channel define one of 16 delay states/360 (or 22.5/step) selectable with the PHx0 to PHx3. The reset input is used to synchronize AD8333s used in arrays.
VPOS VPOS ENBL PH10 PH11 RFIN I1NO RFIP
For optimum performance, the 4LOx inputs are driven differentially but can also be driven single ended. A good choice for a drive is an LVDS device. The common-mode range on each pin is approximately 0.2 V to 3.8 V with nominal 5 V supplies. The minimum LO level is frequency dependent (see Figure 22). For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to assure stable mixer-core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8333 can be operated to very low frequencies at the LO inputs if a square wave is used to drive the LO. Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin (RSET) is provided to synchronize the 4LOx divider circuits when the AD8333s are used in arrays. The RSET pin resets the counters to a known state after power is applied to multiple AD8333s. A logic input must be provided to the RSET pin when using more than one AD8333. See the Reset Input section for more details.
32
31
30
29
28
27
26
25
PH12 1 PH13 2 COMM 3 4LOP 4
BIAS CHANNEL 1 SEL LOGIC 0
24 I1PO 23 Q1PO 22 Q1NO
AD8333
90 BUF /4 90 0 CHANNEL 2 SEL LOGIC
I/Q DEMODULATOR AND PHASE SHIFTER
The I/Q demodulators consist of double-balanced Gilbert cell mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented to the mixers, which convert them to baseband: RF - LO and RF + LO. The signals are phase shifted according to the code applied to Pin PHx0 to Pin PHx3 (see Table 4). The phase shift function is an integral part of the overall circuit (patent pending). The phase shift listed in Column 1 of Table 4 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to the RF inputs of an AD8333, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1 by 22.5. Following the phase shift circuitry, the differential current signal is converted from differential to single ended via a current mirror. An external transimpedance amplifier is needed to convert the I and Q outputs to voltages.
21 VNEG 20 COMM 19 Q2NO 18 Q2PO 17 I2PO
4LON 5 LODC 6 PH23 7 PH22 8
9
10
11
12
13
14
15
16
05543-057
VPOS
RF2P
VPOS
RF2N
RSET
PH21
Figure 52. Block Diagram and Pinout
Each of the current formatted I and Q outputs sum together for beamforming applications. Multiple channels are summed and converted to a voltage using a transimpedance amplifier. If desired, channels can also be used individually.
QUADRATURE GENERATION
The internal 0 and 90 LO phases are digitally generated by a divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LOx inputs. Furthermore, the divider is implemented such that the 4LOx signals reclock the final flip-flops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry.
PH20
I2NO
Rev. A | Page 17 of 28
AD8333
Table 4. Phase Select Code for Channel-to-Channel Phase Shift
-Shift 0 22.5 45 67.5 90 112.5 135 157.5 180 202.5 225 247.5 270 292.5 315 337.5 PHx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PHx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PHx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PHx0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Judicious selection of the RF amplifier ensures the least degradation in dynamic range. The input referred spectral voltage noise density (en) of the AD8333 is nominally 9 nV/Hz to 10 nV/Hz. For the noise of the AD8333 to degrade the system noise figure (NF) by 1 dB, the combined noise of the source and the LNA should be about twice that of the AD8333 or 18 nV/Hz. If the noise of the circuitry before the AD8333 is <18 nV/Hz, then the system NF degrades more than 1 dB. For example, if the noise contribution of the LNA and source is equal to the AD8333, or 9 nV/Hz, the degradation is 3 dB. If the circuit noise preceding the AD8333 is 1.3x as large as that of the AD8333 (or about 11.7 nV/Hz), the degradation is 2 dB. For a circuit noise 1.45x that of the AD8333 (13.1 nV/Hz) degradation is 1.5 dB. To determine the input referred noise, it is important to know the active low-pass filter (LPF) values RFILT and CFILT, shown in Figure 53. Typical filter values (for example, those used on the evaluation board) are 787 and 2.2 nF and implement a 90 kHz single-pole LPF. If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain, from the RF input to the AD8021 output (for example, I1, Q1) is approximately 1.7 x (4.7 dB). This together with the 9 nV/Hz AD8333 noise results in about 15.3 nV/Hz at the AD8021 output. Because the AD8021, including the 787 feedback resistor, contributes another 4.4 nV/Hz, the total output referred noise is about 16 nV/Hz. This value can be adjusted by increasing the filter resistor while maintaining the corner frequency, thereby increasing the gain. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this instance the AD8021.
DYNAMIC RANGE AND NOISE
Figure 53 is an interconnection block diagram of the AD8333. For optimum system noise performance, the RF input signal is provided by a very low noise amplifier, such as the LNA of the AD8332 or the preamplifier of the AD8335. In beamformer applications, the I and Q outputs of a number of receiver channels are summed (for example, the two channels illustrated in Figure 53). The dynamic range of the system increases by the factor 10log10(N), where N is the number of channels (assuming random uncorrelated noise.) The noise in the two channel example of Figure 53 is increased by 3 dB while the signal doubles (6 dB), yielding an aggregate SNR improvement of (6 - 3) = 3 dB.
TRANSMITTER T/R SW TRANSDUCER RFB
AD8332 LNA OR AD8335 PREAMP
CH1 RF
CH1 PHASE SELECT 2 4 2 2 2 2 2 4 CH2 PHASE SELECT 2 2 2 2 I1 * CFILT RFILT I ADC 16-BIT I DATA 570kSPS
AD8333
0
90 CLOCK GENERATOR /4 90
Q1
AD8021
CFILT * RFILT Q
Q2
AD7665 OR AD7686
ADC 16-BIT 570kSPS Q DATA
0
I2
AD8021
CH2 RF TRANSMITTER T/R SW TRANSDUCER RFB
AD8332 LNA OR AD8335 PREAMP
*UP TO 8 CHANNELS PER AD8021
Figure 53. Interconnection Block Diagram
Rev. A | Page 18 of 28
05543-038
AD8333
SUMMATION OF MULTIPLE CHANNELS (ANALOG BEAMFORMING)
Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD8333 is in analog beamforming circuits for ultrasound. Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal, and then combining all channels. The AD8333 provides the means to implement this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar. The AD8333 integrates the phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. To illustrate, Figure 54 is a simplified diagram showing two channels. The ultrasound wave USW is received by two transducer elements, TE1 and TE2, in an ultrasound probe and generates signals E1 and E2. In this example, the phase at TE1 leads the phase at TE2 by 45.
TRANSDUCER ELEMENTS TE1 AND TE2 CONVERT USW TO ELECTRICAL AD8332 USW AT TE1 SIGNALS LEADS USW ES1 LEADS AT TE2 BY ES2 BY 45 19dB 45 45 LNA E1 E2 19dB LNA CH 2 PHASE LEAD 45
PHASE COMPENSATION AND ANALOG BEAMFORMING
Modern ultrasound machines used for medical applications employ a 2n binary array of receivers for beamforming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), while the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain, and the means to sum the individual signals into a composite whole. In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the receive frequency (RF) through the delay line, and then the signal is downconverted by a very large dynamic range I/Q demodulator. The resultant I and Q signals are filtered and sampled by two high resolution ADCs. The sampled signals are processed to extract the relevant Doppler information.
PHASE BIT SETTINGS CH 1 REF (NO PHASE LEAD)
AD8333
S1 AND S2 ARE NOW IN PHASE S1 S2
SUMMED OUTPUT S1 + S2
Figure 54. Simplified Example of the AD8333 Phase Shifter
In a real application, the phase difference depends on the element spacing, (wavelength), speed of sound, angle of incidence, and other factors. The signals ES1 and ES2 are amplified 19 dB by the low noise amplifiers in the AD8332. For optimum signal-to-noise performance, the output of the LNA is applied directly to the input of the AD8333. To sum the signals ES1 and ES2, ES2 is shifted 45 relative to ES1 by setting the phase code in Channel 2 to 0010. The phase-aligned current signals at the output of the AD8333 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 3 dB for the sum of two channels.
Rev. A | Page 19 of 28
05543-063
AD8333
CHANNEL SUMMING
In a beamformer using the AD8333, the bipolar currents at the I and Q outputs are summed directly. Figure 55 illustrates 16 summed channels (for clarity shown as current sources) as an example of an active current summing circuit using the AD8333, AD8021s as first-order current summing circuits, and AD797s as low noise second-order summing circuits. Beginning with the op amps, there are a few important considerations in the circuit shown in Figure 55. The op amps selected for the first-order summing amplifiers must have good frequency response over the full operating frequency range of the AD8333s and be able to source the current required at the AD8333 I and Q outputs. The total current of each of the AD8333s is 6.6 mA for the multiples of the 45 phase settings (Code 0010, Code 0110, Code 1010, and Code 1110) and divided about equally between the baseband frequencies (including a dc component) and the second harmonic of the local oscillator frequency. The desired CW signal tends to be much less (<40 dB) than the unwanted interfering signals. When determining the large signal requirements of the first-order summing amplifiers and lowpass filters, the very small CW signal can be ignored. The number of channels that can be summed is limited by the output drive current capacity of the op amp selected: 60 mA to 70 mA for a linear output current for 5 V and 12 V, respectively, for the AD8021. Because the AD8021 implements an active LPF together with R1 and C1, it must absorb the worst-case current provided by the AD8333, for example, 6.6 mA. Thus, the maximum number of channels that the AD8021 can sum is 10 for 12 V or eight for 5 V supplies. In practical applications, CW channels are used in powers of two, thus the maximum number per AD8021 is eight. Another consideration for the op amp selected as an I-to-V converter is the compliance voltage of the AD8333 I and Q outputs. The maximum compliance voltage is 0.5 V, and a dc bias must be provided at these pins. The AD8021 active LPF satisfies these requirements; it keeps the outputs at 0 V via the virtual ground at the op amp inverting input while providing any needed dc bias current.
FIRST ORDER SUMMING AMPLIFIERS C1A 18nF R1A 100 LPF1A 88kHz +2.8V BASEBAND SIGNAL +5V
2
EIGHT AD8333 I OR Q OUTPUTS 86.6mA PEAK EACH (IF THE PHASE SETTING IS 45) 3.3mA AT DC + 3.3mA AT 2LO
HPF1A 100Hz
LPF2A 81kHz R3A 698 C3A 5.6nF SECOND ORDER SUMMING AMPLIFIER R4 +10V
- +
0.1F
A
3
C2A R2A 1F 698
AD8021
0.1F
-5V
C1B 18nF R1B 100 +5V
2
2 3
- +
0.1F
AD797 -10V 0.1F
(SAME AS ABOVE) - +
0.1F
B
3
C2B R2B 1F 698
R3B 698 C3B 5.6nF
05543-058
AD8021
0.1F
-5V
Figure 55. A 16-Channel Beamformer
Rev. A | Page 20 of 28
AD8333
As previously noted, a typical CW signal has a large dc and very low frequency component compared to its desired low CW Doppler baseband frequency, and another unwanted component at the 2 x LO. The dc component flows through the gain resistors R1x, while the 2 x LO flows through the capacitors C1x. The smaller desired CW Doppler baseband signal is in the frequency range of 1 kHz to 50 kHz. Because the output current of the AD8333 contains the baseband frequency, a dc component, and the 2 x LO frequency voltages, the desired small amplitude baseband signal must be extracted after a series of filters. These are shown in Figure 55 as LPFn, HPFn, and gain stages. Before establishing the value of CLPF1, the resistor RLPF1 is selected based on the peak operating current and the linear range of the op amp. Because the peak current for each AD8333 is 6.6 mA and there are eight channels to be summed, the total peak current required is 52.8 mA. Approximately half of this current is dc and the other half at a frequency of 2 x LO. Therefore, about 26.4 mA flows through the resistor while the remaining 26.4 mA flows through the capacitor. Resistor R1 was selected as 100 and, after filtering, generates a peak dc and very low frequency voltage of 2.64 V at the AD8021 output. For power supplies of 5 V, 100 is a good choice for R1. However, because the CW signal needs to be amplified as much as possible, and the noise degradation of the signal path minimized, the value of R1 should be as large as possible. A larger supply helps in this regard, and the only factor limiting the largest supply voltage is the required power. For a 10 V supply on the AD8021, R1 can be increased to 301 and realize the same headroom as with a 5 V supply. If a higher value of R1 is used, C1 must be adjusted accordingly (in this example 1/3 the value of the original value) to maintain the desired LPF roll-off. The principal advantage of a higher supply is greater dynamic range, and the trade-off is power consumption. The user must weigh the trade-offs associated with the supply voltage, R1, C1, and the following circuitry. A suggested design sequence is: * Select a low noise, high speed op amp. The spectral density noise (en) should be <2nV/Hz and the 3 dB BW 3 x the expected maximum 2 x LO frequency. Divide the maximum linear output current by 6.6 mA to determine the maximum number of AD8333 channels that can be summed. Select the largest value of R1 that permits the output voltage swing within the power supply rails. Calculate the value of C1 to implement the LPF corner that allows the CW Doppler signal to pass with maximum attenuation of the 2 x LO signal. frequency, typically 100 kHz or less, or, as an example, 88 kHz as shown in Figure 55. A useful equation for calculating C1 is
C1 =
1 2R1 f LPF 1
(1)
As previously mentioned, the AD8333 output current contains a dc current component. This dc component is converted to a large dc voltage by the AD8021 LPF. Capacitor C2 filters this dc component and, with R2 + R3, establishes a high-pass filter with a low frequency cutoff of about 100 Hz. Capacitor C3 is much smaller than C2 and, consequently, can be neglected. C2 can be calculated by C2 = 1 2(R2 + R3) f HPF1 (2)
To achieve maximum attenuation of the 2 x LO frequency, a second low-pass filter, LPF2, is established using the parallel combination of R2 and R3, and C3. Its -3 dB frequency is simply f LPF 2 = 1 2(R2 || R3)C 3 (3)
In the example shown in Figure 55, fLPF2 = 81 kHz. Finally, the feedback resistor of the AD797 must be calculated. This is a function of the input current (number of channels) and the supply voltage. The second-order summing amplifier requires a very low noise op amp, such as the AD797, with 0.9 nV/Hz, because the amplifier gain is determined by Feedback Resistor R4 divided by the parallel combination of the LPF2 resistors seen looking back toward the AD8021s. Referring to Figure 55, the AD797 inband (100 Hz to 88 kHz) gain is expressed as
[(R2A + R3A) || (R2B + R2B)]
R4
(4)
*
The AD797 noise gain can increase to unacceptable levels, because the denominator of the gain equation is the parallel resistance of all the R2 + R3 resistors in the AD8021 outputs. For example, for a 64-channel beamformer, the resistance seen looking back toward the AD8021s is about 1.4 k/8 = 175 . For this reason, the value of (R2x + R3x) should be as large as possible to minimize the noise gain of the AD797. (Note that this is the case for the AD8021 stages because they look back into the high impedance current sources of the AD8333s.) Due to these considerations, it is advantageous to increase the gain of the AD8021s as much as possible, because the value of (R2x + R3x) can be increased proportionally. Resistors (R2x + R3x) convert the CW voltages to currents that are summed at the inverting inputs of the AD797 op amp and amplified and converted to voltages by R4.
* *
The filter LPF1 establishes the upper frequency limit of the baseband frequency and is selected well below the 2 x LO
Rev. A | Page 21 of 28
AD8333
The value of R4 needs to be chosen iteratively as follows: * Determine the number of AD8021 first-order summing amplifiers. In Figure 55, there are two; for a 32-channel beamformer, there would be four, and for a 64-channel beamformer, there would be eight. * Determine the output noise after the AD8021s. A first-order calculation can be based on a value of AD8333 output current noise of about 20 pA/Hz. For the values in Figure 55, this results is about 6 nV/Hz for eight channels after the AD8021s. Adding the noise of the AD8021 and the 100 feedback resistor results in about 6.5 nV/Hz total noise after the AD8021 LPF in the CW Doppler band. * Determine the noise of the circuitry after the AD797 and the desired signal level. * Determine the voltage and current noise of the second-order summing amplifiers. * Choose a value for R2x + R3x and for R4. Determine the resulting output noise after the AD797 for one channel and then multiply by the square root of the number of summed AD8021s. Next, check AD797 output noise (both current and voltage noise). Ideally, the sum of the noise of the resistors and the AD797 is less than a factor-of-3 than the noise due to the AD8021 outputs. * Check the following stages output noise against the calculated noise from the combiner circuit and AD8333s; ideally the noise from the following stage should be less than 1/3 of the calculated noise. * If the combined noise is too large, experiment with increasing/decreasing values for R2x + R3x and R4. To simplify, the user can also simulate or build a combiner circuit for optimum performance. It should be noted that the ~20 pA/Hz out of the AD8333 is for the AD8333 with shorted RF inputs. In an actual system, the current noise out of the AD8333 is most likely dominated by the noise from the AD8332 LNA and the noise from the source and other circuitry before the LNA. This helps ease the design of the combiner. The preceding procedures for determining the optimum values for the combiner are based on the noise floor of the AD8333 only. As an example, for a 32-channel beamformer using four lowpass filters, as shown in Figure 55, (R2x + R3x) = 1.4 k and R4 = 6.19 k. The theoretical noise increase of N is degraded by only about 1 dB.
IxNO QxNO
The summed signal level increases by a factor of N while the noise increases only as N. In the case of 64 channels, this is an increase in dynamic range of 18 dB. Note that the AD8333 dynamic range is already about 160 dB/Hz; the summed dynamic range is 178 dB/Hz (equivalent to about 29.5 b/Hz). In a 50 kHz noise bandwidth, this is 131 dB (21.7 bits).
DISABLING THE CURRENT MIRROR AND DECREASING NOISE
The noise contribution of the AD8333 can potentially be reduced if the current mirrors that convert the internal differential signals to single ended are bypassed (see Figure 56). Current mirrors interface to the AD8021 I-V converters shown in Figure 53, and output capacitors across the positive and negative outputs provide low-pass filtering. The AD8021s force the AD8333 output voltage to 0 V and process the bipolar output current; however, the internal current mirrors introduce a significant amount of noise. This noise can be reduced if they are disabled and the outputs externally biased. The mirrors are disabled by connecting VNEG to ground and providing external bias networks, as shown in Figure 56. The larger the drop across the resistors, the less noise they contribute to the output; however, the voltage on the IxxO and QxxO nodes cannot exceed 0.5 V. Voltages exceeding approximately 0.7 V turn on the PNP devices and forward bias the ESD protection diodes. Inductors provide an alternative to resistors, enabling reduced static power by eliminating the power dissipation in the bias resistors.
COMM
OTHER CHANNELS
I-V I-V
IxPO QxPO
VNEG1
1NOTE
THAT PIN VNEG AND PIN COMM ARE CONNECTED TOGETHER.
Figure 56. Bypassing the Internal Current Mirrors
DYNAMIC RANGE INFLATION
Although all 64 channels could theoretically be summed together at a single amplifier, it is important to realize that the dynamic range of the summed output increases by 10xlog10(N) if all channels have uncorrelated noise, where N is the number of channels to be summed.
With inductors, the main limitation might be low frequency operation, as is the case in CW Doppler in ultrasound where the frequency range of interest goes from a few hundred Hertz to about 30 kHz. In addition, it is still important to provide enough gain through the I-to-V circuitry to ensure that the bias resistor and I-to-V converter noise do not contribute significantly to the noise from the AD8333 outputs. Another approach could be to provide a single external current mirror that combines all channels; it would also be possible to implement a high-pass filter with this circuit to help with offset and low frequency reduction.
Rev. A | Page 22 of 28
05543-039
AD8333
The main disadvantage of the external bias approach is that now two I-V amplifiers are needed because of the differential output (see Figure 56). For beamforming applications, the outputs would still be summed as before but now there is twice the number of lines. Only two bias resistors are needed for all outputs that are connected together. The resistors are scaled by dividing the value of a single output bias resistor through N, the number of channels connected in parallel. The bias current depends on the phase selected: for phase 0, this is about 2.5 mA per side, while in the case of 45, this is about 3.5 mA per side. The bias resistors should be chosen based on the larger bias current value of 3.5 mA and the chosen VNEG. VNEG should be at least -5 V and can be larger for additional noise reduction. Excessive noise or distortion at high signal levels degrades the dynamic range of the signal. Transmitter leakage and echoes from slow moving tissue generate the largest signal amplitudes in ultrasound CW Doppler mode and are largest near dc and at low frequencies. A high-pass filter introduced immediately following the AD8333 reduces the dynamic range. This is shown by the two coupling capacitors after the external bias resistors in Figure 56. Users have to determine what is acceptable in their particular application. Care must be taken in designing the external circuitry to avoid introducing noise via the external bias and low frequency reduction circuitry.
Rev. A | Page 23 of 28
AD8333 APPLICATIONS
The AD8333 is the key component of a phase-shifter system that aligns time-skewed information contained in RF signals. Combined with a variable gain amplifier (VGA) and low noise amplifier (LNA), the AD8333 forms a complete analog receiver for a high performance ultrasound system. Figure 57 is a block diagram of a complete receiver using the AD8333 and the AD8332 family.
LNA1 FROM TRANSDUCER T/R SWITCH LNA2 FROM TRANSDUCER T/R SWITCH
AD8332
The rising edge of the active high RSET pulse can occur at any time; however, the duration must be 300 ns minimum (tPW-MIN). When the RSET pulse transitions from high to low, the LO dividers are reactivated; however, there is a short delay until the divider recovers to a valid state. To guarantee synchronous operation of an array of AD8333s, the 4 LO clock must be disabled when the RSET transitions high and remain disabled for at least 300 ns after RSET transitions low.
4 x LO RSET
I1 Q1 16-BIT ADC PROCESSOR
AD8333
I2 Q2 16-BIT ADC PROCESSOR
tPW-MIN
THE TIMING OF THE RISING EDGE OF RSET IS NOT CRITICAL AS LONG AS THE tPW-MIN IS SATISFIED
tHOLD
tHOLD = HOLD TIME tPW-MIN = MINIMUM PULSE WIDTH
05543-059
HS ADC
PROCESSOR
Figure 58. Timing of the RSET Signal to 4 LO
Figure 57. Block Diagram--Ultrasound Receiver Using the AD8333 and AD8332 LNA
Synchronization of multiple AD8333s can be checked as follows: * Set the phase code of all AD8333 channels the same, for example, 0000. * Apply a test signal to a single channel that generates a sine wave in the baseband output and measure the output. * Apply the same test signal to all channels simultaneously and measure the output. * Since all the phase codes of the AD8333s are the same, the combined signal should be N times bigger than the single channel. The combined signal is less than N times one channel if any of the LO phases of individual AD8333s are in error.
As a major element of an ultrasound system, it is important to consider the many I/O options of the AD8333 necessary to perform its intended function. Figure 61 shows the basic connections.
LOGIC INPUTS AND INTERFACES
The logic inputs of the AD8333 are all bipolar-level sensitive inputs. They are not edge triggered, nor are they to be confused with classic TTL or other logic family input topologies. The voltage threshold for these inputs is VPOS x 0.3, so for a 5 V supply the threshold is 1.5 V, with a hysteresis of 0.2 V. Although the inputs are not of themselves logic inputs, any 5 V logic family can drive them.
CONNECTING TO THE LNA OF THE AD8331/ AD8332/AD8334/AD8335 VGAs
+5V
RESET INPUT
The RSET pin is used to synchronize the LO dividers in AD8333 arrays. Because they are driven by the same internal LO, the two channels in any AD8333 are inherently synchronous. However, when multiple AD8333s are used, it is possible that their dividers wake up in different phase states. The function of the RSET pin is to phase align all the LO signals in multiple AD8333s. The 4 x LO divider of each AD8333 can initiate in one of four possible states 0, 90, 180, and 270. The internally generated I/Q signals of each AD8333 LO is always at a 90 angle relative to each other, but a phase shift can occur during power up between the internal LOs of the different AD8333s. The RSET pin provides an asynchronous reset of the LO dividers by forcing the internal LO to hang. This mechanism also allows the measurement of nonmixing gain from the RF input to the output.
Rev. A | Page 24 of 28
RFxP
AD8332
LNA
AD8333
RFxN
05543-061
-5V
Figure 59. Connecting the AD8333 to the LNA of an AD8332
The RFxx inputs (Pin 12, Pin 13, Pin 28, and Pin 29) are optimized for maximum dynamic range when dc-coupled to the differential output pins of the LNA of the AD8331/AD8332/ AD8334 or the AD8335 series of variable gain amplifiers and can be connected directly, as shown in Figure 59.
05543-060
HS ADC
PROCESSOR
AD8333
If amplifiers other than the AD8332 LNA are connected to the input, attention must be paid to their bias and drive levels. For maximum input signal swing, the optimum bias level is 2.5 V, and the RF input must not exceed 5 V to avoid turning on the ESD protection circuitry. If ac coupling is used, a bias circuit, such as that illustrated in Figure 60, is recommended. An internal bias network is provided, however, additional external biasing can center the RF input at 2.5 V.
+5V
The graphs shown in Figure 22 and Figure 23 show the range of common-mode voltages and useable LO levels when the LO input is driven with a single-ended sine wave. Logic families, such as TTL or CMOS, are unsuitable for direct coupling to the LO input.
EVALUATION BOARD
Figure 61 and Figure 62 show the evaluation board schematics; they include an AD8332 to allow tests either directly, as one would use it in an actual application, or by applying signals via connectors directly to the RF inputs. For best performance, it is recommended that the RF inputs be driven differentially. Although the 4 x LO input can be driven single-ended, differential drive is recommended. The 4 x LO inputs require very low bias currents and can be supplied by a multidrop LVDS driver, LV-PECL, or any other high speed differential signal that stays within the common-mode range of the inputs (0.2 V to 3.8 V).
5.23k 1.4k 0.1F RF IN 0.1F RFxN 1.4k 3.74k -5V
05543-062
AD8333
RFxP
Figure 60. AC Coupling the AD8333 RF Input
LO INPUT
The local oscillator (LO) input is a high speed, fully differential, analog input that responds to differences in the input levels (and not logic levels). The LO inputs can be driven with a low common-mode voltage amplifier, such as the National DS90C401 LVDS driver.
VPOS CHANNEL 1 - RF IN + CHANNEL 1 PHASE SELECT BITS
1 31 30 29 28 27 26
120nH FB +5V 0.1F
32 25
VPOS
VPOS
ENBL
RFIP
PH10
RFIN
*
33.2k + LOCAL OSC - 0.1F 0.1F 31.6k
+5V 33.2k
PH11 PH12 PH13 COMM 4LOP 4LON LODC PH23
I1N0 I1PO Q1PO Q1NO
24 23 22 21 20 19 18 17
2 3 4 5
CHANNEL 1 + I OUT CHANNEL 1 + Q OUT 120nH FB -5V 0.1F CHANNEL 2 + Q OUT CHANNEL 2 + I OUT
AD8333
VNEG COMM Q2NO Q2PO
31.6k
0.1F 6
7 8
VPOS
VPOS
14
PH22 PH21
9
RSET
15
RF2N
RF2P
PH20
I2PO I2NO
16
CHANNEL 2 PHASE SELECT BITS - + CHANNEL 2 RF IN
10
11
12
13
0.1F VPOS
Figure 61. AD8333 Basic Connections
Rev. A | Page 25 of 28
05543-040
*OPTIONAL BIAS NETWORK. THESE COMPONENTS MAY BE DELETED IF THE LO IS DC-COUPLED FROM AN LVDS SOURCE BIASED AT 1.2V.
RESET INPUT
+5V GND1 GND2 GND3 GND4 +5V -5V + R26 20 - A1 AD8021 +
4 5 6
AD8333
-5V R39 787 C26 2.2nF
2 1 7
+5VS L6 120nH FB C44 0.1F
C7 10F 10V + TP6 TP5 +5VS
3 8
C8 10F 10V R32 0 I1
R25 20 SW5
L7 C27 5pF 120nH FB C45 0.1F
-5V
SW6 SW15 SW7 C24 0.1F C14 0.1F VPS SW8 VPOS C46 0.1F +5VS
L3 120nH FB
-5VS
R40 787 C29 2.2nF
2
R9 274
32 30 32 31 30 29 28 27 26 25 31 29 28 27 26 25
-
1 8
7
C39 0.018F LOP1 ENBV PH11 I1N0 I2PO Q1PO Q1NO
A2 AD8021
24 23 22 21 3
6 5
R33 0 +
Q1
VIN1
HILO
RFIP RFIN
VCM1
ENBL
PH10
VPOS
COM1
VPOS
LON1
2
COMM VOH1 VOL1 VPSV NC VOL2 VOH2
18 19 6 20 21 22 23 2
+5V PH12 PH13 COMM 4LOP 4LON LODC PH23
ENBL
TP4
24 1
VIP1
C1 0.1F
1
4
C28 5pF -5VS R4 OPT VNEG COMM Q2NO Q2PO
20 19 18 17
L1 120nH FB VPS1
3
C2 22pF L5 120nH FB
3 4
VPS INH1
4
TP3 C42 0.1F C43 1nF
5
C47 0.1F
IN1 LMD1 LMD2 INH2 VPS2 C17 0.1F
7 8 5 6 7 8 17
L4 120nH FB -5V C36 0.1F R5 OPT +5VS I2PO C49 0.1F R41 787 C48 0.1F
C6 0.1F
C5 0.1F
Z1 AD8332
AD8333
COM2
VIP2
VIN2
VCM2
MODE
GAIN
PH20
VPOS
RF2P
RF2N
VPOS
Figure 62. AD8333 Evaluation Board Schematic
LOP2
9 10 11 12 13 14 15 16
IN2 C13 0.1F Z3 DS90C401
3 2 4
RCLMP
R1 100
PH21
9
RSET
Rev. A | Page 26 of 28
LON2 COMM PH22
10 11 12 13 14 15
TP2
C4 0.1F
L2 120nH FB
C3 22pF
VPS
TP1
C40 0.018F
I2NO
16
R3 0 R2 0 SW11 VPOS +5V SW23 +5VS
1 8 2 7
C31 2.2nF -
R10 274 C11 0.1F +5V R6 3.48k C9 0.1F
1 7
A3 AD8021
5
6
R35 0 + R7 1.5k SW12 SW13 C41 0.1F R15 OPT R13 49.9 RST
3
Q2
C12 0.1F
4
C30 5pF -5VS C50 0.1F R42 787
Z3 SPARE
8 6 5
LOP R22 20
SW14
+5VS +5V TP7 TP8 C51 0.1F
C32 2.2nF
2 1
-
7
R23 20
+5VS
8 3
A4 AD8021
5
6
R38 0 +
I2
4
C33 5pF -5VS C52 0.1F
05543-042
AD8333 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
12 MAX
9
0.25 MIN 3.50 REF THE EXPOSE PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
041806-A
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8333ACPZ-REEL 1 AD8333ACPZ-REEL71 AD8333ACPZ-WP1, 2 AD8333-EVAL
1
2
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-32-2 CP-32-2 CP-32-2
Z = Pb-free part. WP = Waffle pack.
Rev. A | Page 27 of 28
AD8333 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05543-0-5/06(A)
Rev. A | Page 28 of 28

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